UVM_Q&A.txt - 2015.03.22

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Johan Sandstrom - Verification Engineer for ASIC/SoC/FPGA
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 1.0   Do you have a requirements document with numbers that will be
       referenced by the:
 1.1     Verification Plan?
 1.2     Functional Coverage Plan?
 1.3     Assertion Plan?
 1.4     Error Injection Plan?

 2.0   How do you fold derived requirements into the original requirements
       document?

 3.0   How do you ensure all requirements have been met by their
       requirements reference number?

 4.0   How do you track changes to the requirements?

 5.0   How do you ensure the Customer/Systems/Design/Verification teams
       are on the same page?
 5.1     When checking in files to your version control tool do you
         have a 'continuous integration' methodology (gatekeeper)?
 5.2     Do you email team members when checking in files?

 6.0   What bug tracking tool do you use?

 7.0   If not pure SV/UVM what other 'tools' are in your verification
       flow?

 8.0   Do you adhere to the Guidelines and Rules in the UVM Cookbook?
 8.1     Do you adhere to:
           www.doulos.com/knowhow/sysverilog/uvm/easier_uvm_guidelines/detail/
 8.2     Do you have your own SV/UVM coding guidelines?
 8.3     Are the Guidelines and Rules incorporated into your linting tool?

 9.0   Do you have SV/UVM naming conventions?

10.0   Do you make or buy VIP?

11.0   Do you use 'register generation tools' and uvm_reg?

12.0   How do you handle multiple resets in a test?

13.0   How do you test SVAs?

14.0   Which CDC tool do you use?

15.0   Which code coverage tool do you use?

16.0   Do you need emulator-ready UVM?