-------------------------------	-----------------------------------------	-------------------------------------------------
-- model supplier:	Johan Sandstrom	310.977.9435
--		johan@sandstrom.org
-- project:	PreSynth.
-- description:	TestBench showing how to compare the original source to the preprocessed source.
-- filename:	TestBench.vhd
-- yyyy/mm/dd	modifier	Description of change
----------------	-------------	-------------------------------------------------
-- 1997/10/24	johan	Initial release
-------------------------------	-----------------------------------------	-------------------------------------------------

library ieee; use ieee.std_logic_1164.all;

entity TestBench is end;

architecture example of TestBench is

  component source
    port (some_inputs    : in    std_logic;
              some_outputs : out std_logic);
  end component;

  component source_PS
    port (some_inputs    : in    std_logic;
              some_outputs : out std_logic);
  end component;

  signal some_inputs                          : std_logic;
  signal some_outputs_source         : std_logic;
  signal some_outputs_source_PS  : std_logic;
  signal stimulus_from_somewhere : std_logic;

begin

  i1 : source
    port map(some_inputs    => some_inputs,
                     some_outputs => some_outputs_source);

  i2 : source_PS
    port map(some_inputs    => some_inputs,
                     some_outputs => some_outputs_source_PS);

  some_inputs <= stimulus_from_somewhere;

  assert (some_outputs_source = some_outputs_source_PS) report
    "source differs from source_PS" severity warning;

end example;