310.977.9435

johan@sandstrom.org

www.sandstrom.org

 

ASIC and FPGA Designer:     Johan Sandstrom   -   2010 resume

Experience Overview:

(Consultant/Contractor/JobShopper)

Senior level designer of digital electronic equipment;
ASIC/FPGA, VHDL/Verilog/SystemVerilog models.

Good balance of commercial/military/aerospace experience and the wherewithal to
successfully complete projects.

"Comparing Verilog to VHDL Syntactically and Semantically" authored in 1995.

 

Tools:

 

Languages:

C, Perl, PSL, Tcl, Verilog, OVM/SystemVerilog, VHDL.

Simulators:

Aldec, Cadence, Ikos, Modelsim, Synopsys, Vantage.

Synthesis:

Altera Quartus, Synopsys, Synplicity, Xilinx ISE.

DFT:

Mentor, Synopsys.

STA:

PrimeTime, QuickPath.

ASICs/FPGAs:

Actel, Altera, AMCC, AMI, Honeywell, Hughes, IBM,
Lattice, Loral, LSI Logic, Xilinx.

Buses:

DDR-SDRAM, Ethernet (802.3), FireWire (1394), I2C, IBM-360, IEEE-488, ISA, Mil-1553, PCI, PCI Express, PMC, RS-232, SPI, VME.

 

Experience:

 

Since 1992 I've contributed to each project in about the same way:
  1. Become an ASIC/FPGA team member and learn project specifics.
  2. Design all or part of the ASIC/FPGA in some HDL.
    Create HDL macros and scripts for others to use.
  3. Create scripts (Perl, C shell, Tcl, DCSH, DOS bat)
    for all phases of the project.
  4. Synthesize using Synopsys Design Compiler or Synplicity.
  5. Perform ASIC/FPGA verification by creating elaborate
    self-checking TestBenches and PSL.
  6. Add testability (full scan, partial scan, BIST).
  7. Perform Equivalence Checking using Synopsys Formality.
  8. Perform Static Timing Analysis using Synopsys PrimeTime.

 

2006-10

Gen Dynamics

1)  FPGAs for Software Defined Radio.

 

 

2)  FPGAs for SONAR.

2008

Parker-Hannifin

--  FPGA for motor control.

2006

Sandstrom Engr

--  PCI Express behavioral model.

1999-06

Raytheon

1)  FPGA for PCI_Ethernet.

 

 

2)  FPGA & ASIC for PCI_Fibre_Channel .

 

 

3)  FPGA for DDR_SDRAM controller.

 

 

4)  ASIC (Mixed-Signal) for antenna control.

 

 

5)  ASIC for PCI_PowerPC.

2000-01

EDAptive

--  ASIC-to-ASIC porting tool.

1999-00

NASA (JPL)

--  FPGA & ASIC for PCI_1394_I2C_UART.

1998-99

Imperial Tech

--  FPGA for PCI_Memory_Reed-Solomon.

1997-99

Sandstrom Engr

--  Synthesis Pre-processor for VHDL.

1995-00

Hughes (Space)

1)  ASICs (DSP) for satellites.

 

 

2)  SEU and total dose testing.

 

 

3)  Common library development.

1994

Hughes (HRL)

--  Performance model of Image Processor.

1992-95

Hughes (Radar)

1)  ASICs/FPGAs for RADAR.

 

 

2)  Synopsys Logic Modeling for Mil-1553.

1987-92

U.S. Navy

--  C & VHDL simulation for Missile guidance.


                                                                               Back in the day I worked for IBM at Cape Canaveral on the Apollo

                                                                               program; helped design the proton accelerator at Fermi Labs; designed

                                                                               disk controllers for Data General, Digital Equipment Corp and IBM

                                                                               minicomputers; designed computers using the 2901 bit-slice.

 

                                                                                                 *** End of Johan Sandstrom's resume ***




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