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310.977.9435
johan@sandstrom.org
www.sandstrom.org

 

Digital  “Design / UVM Verification”  Consultant  -  2017 resume summary

Experience Overview:

(Consultant since 1982)

Senior level designer of digital electronic equipment;
ASIC/FPGA, VHDL/Verilog/SystemVerilog/UVM models.

Good balance of commercial/military/aerospace experience and the wherewithal to
successfully complete projects.

"Comparing Verilog to VHDL Syntactically and Semantically" authored in 1995.

 

Tools:

Languages:

C, Perl, PSL, Tcl, Verilog, SystemVerilog/UVM, VHDL.

Simulators:

Aldec, Cadence, Ikos, Modelsim, Synopsys, Vantage.

Synthesis:

Altera, Synopsys, Synplicity, Xilinx.

DFT:

Mentor, Synopsys.

STA:

PrimeTime, QuickPath.

ASICs/FPGAs:

Actel, Altera, AMCC, AMI, Honeywell, Hughes, IBM,
Lattice, Loral, LSI Logic, TSMC, Xilinx.

Buses:

AXI, DDR-SDRAM, Ethernet (802.3), FireWire (1394), I2C, IBM-360, IEEE-488, ISA, Mil-1553, PCI, PCIe, PMC, RS-232, SPI, VME.

 

Experience:

Since 1992 I've contributed to each project in about the same way:

  1. Become an ASIC/FPGA team member and learn project specifics.
  2. Design all or part of the ASIC/FPGA in some HDL.
    Create HDL macros and scripts for others to use.
  3. Create scripts (Perl, C shell, Tcl, DCSH, DOS bat)
    for all phases of the project.
  4. Synthesize using Synopsys Design Compiler or Synplicity.
  5. Perform ASIC/FPGA verification by creating elaborate
    self-checking TestBenches and UVM.
  6. Add testability (full scan, partial scan, BIST).
  7. Perform Equivalence Checking using Synopsys Formality.
  8. Perform Static Timing Analysis using Synopsys PrimeTime.

 

2015-17

Micron

1)  ASIC for Machine Learning.

2015

Lockheed Martin

1)  FPGA for 'Nuclear Protection and Control'.

2014

Harris

1)  ASIC for XAUI communication satellite.

2013

Qualcomm

1)  ASIC for Power Management.

2012-13

STMicroelectronics

1)  ASIC for DOCSIS 3.1 Upstream PHY.

2012

Intel

1)  SoC for Graphics Engine.

2011

SEAKR

1)  ASIC for Iridium satellite update.

2006-10

Gen Dynamics

1)  FPGAs for SONAR.

 

2)  FPGAs for Software Defined Radio.

2008

Parker-Hannifin

1)  FPGA for motor control.

2006

Sandstrom Engr

1)  PCI Express behavioral model.

1999-06

Raytheon

1)  FPGA for PCI_Ethernet.

 

2)  FPGA & ASIC for PCI_Fibre_Channel .

 

3)  FPGA for DDR_SDRAM controller.

 

4)  ASIC (Mixed-Signal) for antenna control.

 

5)  ASIC for PCI_PowerPC.

2000-01

EDAptive

1)  ASIC-to-ASIC porting tool.

1999-00

NASA (JPL)

1)  FPGA & ASIC for PCI_1394_I2C_UART.

1998-99

Imperial Tech

1)  FPGA for PCI_Memory_Reed-Solomon.

1997-99

Sandstrom Engr

1)  Synthesis Pre-processor for VHDL.

1995-00

Hughes (Space)

1)  ASICs (DSP) for satellites.

2)  SEU and total dose testing.

3)  Common library development.

1994

Hughes (HRL)

1)  Performance model of Image Processor.

1992-95

Hughes (Radar)

1)  ASICs/FPGAs for RADAR.

2)  Synopsys Logic Modeling for Mil-1553.

1987-92

U.S. Navy

1)  C & VHDL simulation for Missile guidance.

1984-87

Perkin-Elmer

1)  VHSIC E-Beam machine test equipment.

1983

Cipher Data

1)  IBM tape controller using Z80.

1982-84

Hughes (HRL)

1)  VHSIC E-Beam machine development.

1982

Racal-Dana

1)  Switch Controller using 6809 & IEEE488.

1980-82

Northrop

1)  Emulated 68000 with 2901 bit-slice.

1977-80

Perkin-Elmer

1)  Disk application engineer.

 

 

2)  Disk test system with 2901 bit-slice.

1972-77

General Instrument

1)  Disk controllers for minicomputers.

1970-71

FermiLabs

1)  Radiation safety equipment.

 

 

2)  Proton accelerator.

1967-70

General Instrument

1)  Disk intercouplers for minicomputers.

1965-67

IBM

1)  Apollo program at Cape Canaveral.






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