1. Comparing Verilog to VHDL Syntactically and Semantically
    (Integrated System Design - October 1995)

  2. Controlling STD_LOGIC_ARITH Warning Messages
    (SNUG ´97)

  3. EDA Software -- 'Presynth.vhd' touted for ability to write at higher level than synthesis tools permit -- Designer crafts synthesis preprocessor to check VHDL code
    (EETimes - February 16, 1998)

  4. Formal Verification Helps Stamp Out Design Bugs
    (Electronic Design - December 1, 1998)

  5. Soaring circuit complexity is the attractive force that keeps HDL add-in tools ...
    (isd - June 1999)


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