1. Comparing Verilog to VHDL Syntactically and Semantically
    (Integrated System Design - October 1995)

  2. Controlling STD_LOGIC_ARITH Warning Messages
    (SNUG ´97)

  3. Free Delivery of Your Sailboat
    (2003.07.23)

  4. Rescue Medal
    (2004.05.15)

  5. Startup Bug with the Xilinx SRL16
    (2008.11.09)

  6. Phone Number Styles
    (2009.09.29)

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