1) Start with leaf-level entity/architectures and work your way up; just like 
    synthesis. (See example source.) 

2) Write a TestBench that instantiates both your design and the to-be-created 
    design_PS. (See example TestBench.) Simulate your design in this environment. 

3) Write a configuration, PS_cfg.vhd, that tells PreSynth.vhd the name of the file to
    read, the name of the file to write, and the name of your clock. (See example 
    PS_cfg.) 

4) Analyze PreSynth.vhd.

5) Analyze PS_cfg.vhd. 

6) Elaborate and simulate PS_cfg for 100 ns. (Simulation time only advances a 
    few ns.) File source_PS.vhd is created. (See example source_PS.) 

   6a) Any errors in your source are displayed in the simulator transcript  
         window and annotated in source_PS.vhd. You MUST fix your code. 

   6b) Any warnings about your source are displayed in the simulator transcript 
         window and annotated in source_PS.vhd. You SHOULD fix your code. 

   6c) Any messages are annotated in source_PS.vhd. You might have a look at 
         the messages if you have time. 

7) Analyze source_PS.vhd 

8) Re-run the TestBench, but this time enable the comparison between the original 
    design "source" and the modified design "source_PS". 

   8a) Miscompares might be due to the dreaded "reset problem", or perhaps 'left 
         (tick left) problem(s). Throughly understand any miscompares before 
         proceeding. This is a good place for a design review. 

9) Synthesize source_PS.vhd.